Results - EEDG 6301 - UTD TRENDS

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Advanced Digital Logic

EEDG 6301

Erik Jonsson School of Engineering and Computer Science

Modern design techniques for digital logic. Logic synthesis and design methodology. Link between front-end and back-end design flows. Field programmable gate arrays and reconfigurable digital systems. Introduction to testing, simulation, fault diagnosis and design for testability. 3 credit hours.

Prerequisites: EE 3320 or equivalent and background in VHDL/Verilog.

Offering Frequency: Every two years

Grades: 249

Median GPA: A

Mean GPA: 3.784

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