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5.0
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5.0
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1,000
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99%
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Search Results
| Name | Grades | Rating | |||
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Not teaching in Spring 2026 | |||||
EEDG 6370 Benjamin Carrion Schaefer | |||||
A- | |||||
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| Name | Grades | Rating | |||
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Not teaching in Spring 2026 | |||||
EEDG 6370 Benjamin Carrion Schaefer | |||||
A- | |||||
Benjamin Carrion Schaefer
[email protected]Grades: 577
Median GPA: B+
Mean GPA: 3.309
4.4
Professor rating
3.8
Difficulty
31
Ratings given
81%
Would take again
Design and Analysis of Reconfigurable Systems
EEDG 6370
Erik Jonsson School of Engineering and Computer Science
Introduction to reconfigurable computing. Review different programmable architectures. Software environments for reconfigurable systems and CAD flow, including High-level Synthesis (HLS), logic synthesis, technology mapping, and place and route. Emphasis on using ANSI-C, C++, or SystemC instead of Verilog or VHDL. Theory of HLS process including technology independent optimizations, resource allocation, scheduling, and binding stages. Use of FPGAs in applications including emulation, data centers, custom computing, and embedded application-based computing. Students will design different hardware accelerators using HLS and prototype them on an FPGA. 3 credit hours.
Prerequisite: EE 3320 or equivalent.
Offering Frequency: Based on student interest and instructor availability
Grades: 88
Median GPA: A-
Mean GPA: 3.572
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Benjamin Carrion Schaefer
[email protected]Grades: 577
Median GPA: B+
Mean GPA: 3.309
4.4
Professor rating
3.8
Difficulty
31
Ratings given
81%
Would take again
Design and Analysis of Reconfigurable Systems
EEDG 6370
Erik Jonsson School of Engineering and Computer Science
Introduction to reconfigurable computing. Review different programmable architectures. Software environments for reconfigurable systems and CAD flow, including High-level Synthesis (HLS), logic synthesis, technology mapping, and place and route. Emphasis on using ANSI-C, C++, or SystemC instead of Verilog or VHDL. Theory of HLS process including technology independent optimizations, resource allocation, scheduling, and binding stages. Use of FPGAs in applications including emulation, data centers, custom computing, and embedded application-based computing. Students will design different hardware accelerators using HLS and prototype them on an FPGA. 3 credit hours.
Prerequisite: EE 3320 or equivalent.
Offering Frequency: Based on student interest and instructor availability
Grades: 88
Median GPA: A-
Mean GPA: 3.572
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