My PlannerExplore and compare past grades, professor ratings, and reviews to find the perfect class.
Grades:
Median GPA:
Mean GPA:
Search Results
| Name | Grades | Rating |
|---|---|---|
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
Grades:
Median GPA:
Mean GPA:
Search Results
| Name | Grades | Rating |
|---|---|---|
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
Search Results
| Name | Grades | Rating |
|---|---|---|
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
Search Results
| Name | Grades | Rating |
|---|---|---|
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
A+ | ||
Search Results
| Name | Grades | Rating | |||
|---|---|---|---|---|---|
EEDG 6301 (Overall) | |||||
A | |||||
EEDG 6301 William Swartz | |||||
A | |||||
Not teaching in Spring 2026 | |||||
EEDG 6301 Nagendra Gulur | |||||
A- | |||||
EEDG 6301 Mehrdad Nourani | |||||
A- | |||||
Search Results
| Name | Grades | Rating | |||
|---|---|---|---|---|---|
EEDG 6301 (Overall) | |||||
A | |||||
EEDG 6301 William Swartz | |||||
A | |||||
Not teaching in Spring 2026 | |||||
EEDG 6301 Nagendra Gulur | |||||
A- | |||||
EEDG 6301 Mehrdad Nourani | |||||
A- | |||||
Advanced Digital Logic
EEDG 6301
Erik Jonsson School of Engineering and Computer Science
Modern design techniques for digital logic. Logic synthesis and design methodology. Link between front-end and back-end design flows. Field programmable gate arrays and reconfigurable digital systems. Introduction to testing, simulation, fault diagnosis and design for testability. 3 credit hours.
Prerequisites: EE 3320 or equivalent and background in VHDL/Verilog.
Offering Frequency: Every two years
Grades: 311
Median GPA: A
Mean GPA: 3.721
Click a checkbox to add something to compare.
Advanced Digital Logic
EEDG 6301
Erik Jonsson School of Engineering and Computer Science
Modern design techniques for digital logic. Logic synthesis and design methodology. Link between front-end and back-end design flows. Field programmable gate arrays and reconfigurable digital systems. Introduction to testing, simulation, fault diagnosis and design for testability. 3 credit hours.
Prerequisites: EE 3320 or equivalent and background in VHDL/Verilog.
Offering Frequency: Every two years
Grades: 311
Median GPA: A
Mean GPA: 3.721
Click a checkbox to add something to compare.