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Search Results
| Name | Grades | Rating | |||
|---|---|---|---|---|---|
Not teaching in Spring 2026 | |||||
EEDG 5325 (Overall) | |||||
A | |||||
EEDG 5325 William Swartz | |||||
A | |||||
Search Results
| Name | Grades | Rating | |||
|---|---|---|---|---|---|
Not teaching in Spring 2026 | |||||
EEDG 5325 (Overall) | |||||
A | |||||
EEDG 5325 William Swartz | |||||
A | |||||
Hardware Modeling Using HDL
EEDG 5325
Erik Jonsson School of Engineering and Computer Science
This course introduces students to hardware description languages (HDL) beginning with simple examples and describing tools and methodologies. It covers the language, dwelling on fundamental simulation concepts. Students are also exposed to the subset of HDL that may be used for synthesis of custom logic. HDL simulation and synthesis labs and projects are performed using commercial and/or academic VLSI CAD tools. 3 credit hours.
Prerequisite: EE 3320 or equivalent.
Offering Frequency: Every two years
Grades: 129
Median GPA: A
Mean GPA: 3.852
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Hardware Modeling Using HDL
EEDG 5325
Erik Jonsson School of Engineering and Computer Science
This course introduces students to hardware description languages (HDL) beginning with simple examples and describing tools and methodologies. It covers the language, dwelling on fundamental simulation concepts. Students are also exposed to the subset of HDL that may be used for synthesis of custom logic. HDL simulation and synthesis labs and projects are performed using commercial and/or academic VLSI CAD tools. 3 credit hours.
Prerequisite: EE 3320 or equivalent.
Offering Frequency: Every two years
Grades: 129
Median GPA: A
Mean GPA: 3.852
Click a checkbox to add something to compare.