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Search Results
| Name | Grades | Rating | |||
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EECT 6325 (Overall) | |||||
B+ | |||||
EECT 6325 Minah Lee | |||||
Not teaching in Spring 2026 | |||||
EECT 6325 Joseph Friedman | |||||
B+ | |||||
EECT 6325 Ramanathan Ramani | |||||
EECT 6325 Carl Sechen | |||||
B+ | |||||
Search Results
| Name | Grades | Rating | |||
|---|---|---|---|---|---|
EECT 6325 (Overall) | |||||
B+ | |||||
EECT 6325 Minah Lee | |||||
Not teaching in Spring 2026 | |||||
EECT 6325 Joseph Friedman | |||||
B+ | |||||
EECT 6325 Ramanathan Ramani | |||||
EECT 6325 Carl Sechen | |||||
B+ | |||||
VLSI Design
EECT 6325
Erik Jonsson School of Engineering and Computer Science
Introduction to MOS transistors. Analysis of the CMOS inverter. Combinational and sequential design techniques in VLSI; issues in static, transmission gate and dynamic logic design. Design and layout of complex gates, latches and flip-flops, arithmetic circuits, memory structures. Low power digital design. The method of logical effort. CMOS technology. Use of CAD tools to design, layout, check, extract and simulate a small project. 3 credit hours.
Prerequisites: EE 3301 and EE 3320 or equivalent.
Offering Frequency: Each semester
Grades: 413
Median GPA: B+
Mean GPA: 3.328
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VLSI Design
EECT 6325
Erik Jonsson School of Engineering and Computer Science
Introduction to MOS transistors. Analysis of the CMOS inverter. Combinational and sequential design techniques in VLSI; issues in static, transmission gate and dynamic logic design. Design and layout of complex gates, latches and flip-flops, arithmetic circuits, memory structures. Low power digital design. The method of logical effort. CMOS technology. Use of CAD tools to design, layout, check, extract and simulate a small project. 3 credit hours.
Prerequisites: EE 3301 and EE 3320 or equivalent.
Offering Frequency: Each semester
Grades: 413
Median GPA: B+
Mean GPA: 3.328
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